1. Field of the Invention
The present invention relates to a voltage converter and a method of converting a voltage, and more particularly, to a high-speed and low-power voltage level converter circuit and method for performing the same.
2. Description of the Relate Art
Power consumption may be an issue for portable electronic systems. In CMOS circuits, it is known that the power consumption is proportional to the square of a supply voltage. With a quadratic relationship to power, lowering voltage offers an effective way of reducing power consumption. However, a penalty of lowering voltage may be increased propagation delay.
Conventional techniques to reduce supply voltage without degrading the performance are available. To achieve high-speed operation and/or low-power consumption, a multiple supply voltage (MSV) is frequently used. In MSV, however, a current flowing directly from the applied voltage source to ground may consume undesirable power for low power applications. A DC current flowing from the supply voltage to the ground voltage may consume relatively high amounts of power, while also increasing the propagation time of the circuit. To remove undesirable power consumption, level converters may be placed between logic circuits.
One example of a conventional method is depicted in FIG. 1. FIG. 1 illustrates a conventional buffer-type level converter (BTLC). Upon transition of an input signal IN from a high level to a low level, an NMOS transistor MN1 is turned off and a voltage node N1 is discharged through an NMOS transistor MN2, causing a PMOS transistor MP1 to turn on. While the node N1 voltage is discharged through the NMOS transistor MN2, a PMOS transistor MP2 is turned on by an output signal OUT supplying a current to the node N1. The PMOS transistor MP2 is turned on until the output signal OUT is sufficiently increased to a high level. Thus, there exists a DC path IDC from a supply voltage VDDH to the input node N1 through the NMOS transistor MN2.
This results in an increase in transition delay of the output signal OUT. This phenomenon may become more serious as a supply voltage VDDL is lowered because a gate-source voltage of the NMOS transistor MN2 is decreased. As the gate-source voltage of the transistor MN2 is decreased, the amount of current flowing via the NMOS transistor MN2 is decreased. This increases the transition delay of the output signal OUT, with the existence of a DC path.
Another example of a conventional method is depicted in FIG. 2. FIG. 2 illustrates a conventional dual cascade voltage switch (DCVS). When an input signal IN is at a low level, node N11 is a low level and node N12 is at a high level. In this condition, when the input signal IN has a low-to-high transition, an NMOS transistor MN12 is turned on and discharges a voltage of the node N12 to a ground voltage. At this time, since a PMOS transistor MP12 is turned on, a DC path is formed between a supply voltage VDDH and a ground voltage. Likewise, when the input signal IN has a high-to-low transition, an NMOS transistor MN11 is turned on, discharging a voltage of the node N11 to a ground voltage. At this time also, since a PMOS transistor MP11 is turned on, a DC path is formed between a supply voltage VDDH and a ground voltage.
This also results in an increase in transition delay of the output signal OUT. This phenomenon may become more serious as a supply voltage VDDL is lowered because a gate-source voltage of the NMOS transistor MN11 is decreased. As the gate-source voltage of the transistor MN11 is decreased, the amount of current flowing via the NMOS transistor MN11 is decreased. This increases the transition delay of the output signal OUT, with the existence of a DC path.
Another example of a conventional method is depicted in FIG. 3. FIG. 3 illustrates a conventional symmetrical dual cascade voltage switch (SDCVS).
The SDCVS in FIG. 3 may be used to reduce transition delay of the DCVS of FIG. 2. This may be accomplished by adding NMOS transistors MN13 and MN14 to turn off the PMOS transistor MP11 or MP12 more quickly at a transition of the input signal IN. However similar to the converter circuit in FIG. 2, the converter circuit in FIG. 3 suffers from DC path problems.
As set forth above conventional converter circuits, such as the BLTC, DCVS and SDCVS circuits described above, have a problem that a transition delay of an output signal becomes longer due to a DC path, or in other words, undesirable power consumption is increased.